Mon, Sept. 4, 9:15-10:15
"All Programmable FPGA, providing hardware efficiency to software programmers", Ivo Bolsens, Xilinx
Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. This dichotomy is driven by, on the one hand , the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All Programmable architecture empowering system and software engineers.
Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP). Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium.
Tue, Sept. 5, 9:00-10:00
"Intel's roadmap and commitment on machine learning/AI", Pradeep Dubey, Intel Labs
New developments in AI are more exciting than ever. The next big wave promises to provide insights at a greater accuracy to help solve some of the world’s biggest challenges. In this talk Pradeep will discuss how Intel is driving AI forward with $the Industry’s most comprehensive road map portfolio to deliver end-to-end AI solutions, and collaborating with thought leaders to address the technical challenges posed by AI.
Pradeep Dubey is an Intel Fellow and Director of Parallel Computing Lab (PCL), part of Intel Labs. His research focus is computer architectures to efficiently handle new compute- and data-intensive application paradigms for the future computing environment. Dubey previously worked at IBM’s T.J. Watson Research Center, and Broadcom Corporation. He has made contributions to the design, architecture, and application-performance of various microprocessors, including IBM® Power PC*, Intel® i386TM, i486TM, Pentium® Xeon®, and the Xeon Phi™ line of processors. He holds over 36 patents, has published over 100 technical papers, won the Intel Achievement Award in 2012 for Breakthrough Parallel Computing Research, and was honored with Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dr. Dubey received a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.
Wed, Sept. 6, 9:00-10:00
"The Era of Accelerators", Viktor K. Prasanna, University of Southern California
This talk will review the promise of reconfigurable computing leading up to current trends in accelerators. We will illustrate FPGA-based parallel architectures and algorithms for a variety of data analytics kernels in advanced networking, streaming graph processing and machine learning. While demonstrating algorithm-architecture co-design methodology to realize high performance accelerators for deep packet inspection, regular expression matching, packet classification, traffic classification, heavy hitter detection, etc., we demonstrate the role of modeling and algorithmic optimizations to develop highly efficient IP cores. We also show high throughput and energy efficient accelerator designs for a class of graph analytics and machine learning kernels. Our approach is based on high level abstractions of the FPGA platforms and design of efficient data structures, algorithms and mapping methodologies. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multi-core processors, FPGAs, GPUs and coherent memory.
Viktor K. Prasanna is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical Engineering and Professor of Computer Science at the University of Southern California. He is the Steering Co-chair of the IEEE International Parallel and Distributed Processing Symposium (www.ipdps.org) and the Steering Chair of the IEEE International Conference on High Performance Computing (www.hipc.org). He is a Fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS). He is a recipient of 2009 Outstanding Engineering Alumnus Award from the Pennsylvania State University. He received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing.
Wed, Sept. 6, 13:00-14:00
"FPGAs in space: current experiences, future challenges and opportunities", David Merodio Codinachs, ESA
FPGAs are key components in space equipment due to their versatility to implement digital functions. They are embarked in satellites and used in many applications; such as observing the earth, provide telecommunications and navigation services as well as to contribute to science and explore the wider Universe. The FPGAs that are used in space have to face very different conditions compared to terrestrial applications, especially due to the radiation environment: that reduces the selection of FPGAs that can survive and provide the functionality during the lifetime of the mission, often limiting the performance and integration that could be achieved with the “terrestrial” state-of-the-art FPGAs.
This talk will provide an overview of the current use of FPGAs in ESA missions and will provide a short introduction to the radiation effects in the FPGAs, how they are analysed, the categories of radiation mitigation techniques used, as well as how this information is used in the FPGA selection for specific missions.
The emerging private space industry or “new space”, as well as, the nanosatellites have different requirements than the class 1 programmes. The points presented are becoming even more relevant and are including new challenges.
David Merodio Codinachs is since 2005 an ASIC/FPGA engineer at the European Space Agency (ESA) in the Technology, Engineering and Quality Directorate. He has been providing support on the use of FPGAs and digital ASICs to several ESA projects and missions, especially for Earth Observation, Telecom and Science. In parallel, he is the ESA Technical Officer of the new radiation hardened (rad-hard) European FPGAs as well as of several ESA R&D contracts mainly focused design mitigation techniques against radiation effects for non rad-hard FPGAs. His interests are in the area of digital microelectronics and design methodologies; with special focus on radiation tolerant systems and reconfigurable computing. David served as the chair, co-chair, and program-chair of the NASA/ESA Conference on Adaptive Hardware (AHS); as technical chair of the 2017 Military and Aerospace Programmable Logic Devices (MAPLD) and as co-organizer of the SpacE FPGA Users Workshop (SEFUW). Prior to joining ESA 12 years ago, he has been working as ASIC design consultant for Alcatel Bell (now Nokia) and Philips (now NXP) for microelectronics designs in telecommunications and medical/audio products. David holds an MSc in electronic engineering from Politecnico di Torino and an MSc in telecommunications engineering from Universitat Politècnica de Catalunya.